The present invention relates to logical integrated circuit (IC) and system LSI chips that are constructed by assembling a plurality of logical blocks into a chip, a method of designing such chips and a method of mass production thereof.
When designing logical IC and system LSI chips, such a design method has conventionally been used that comprises dividing the whole functionalty into multiple functional blocks, designing each block, and assembling all blocks into the chip. A design method reusing functional blocks that have been designed beforehand and retained as Intellectual Properties (IPs) has lately been known. A corporation manufacturing IC and LSI chips may buy such blocks of IPs of another corporation in addition to using in-house designed IPs.
When constructing a system LSI chip by assembling its functional blocks into the chip, it is required for each block that signal inputs and outputs take place in conformity with the block interface specifications to make the functional block properly function, wherein the interface means passing input/output signals from one block to another block and vice versa. As a method of determining whether inputting and outputting signals to/from each functional block conform to the interface specifications, the following method is known. To a logic simulation model for a system LSI as a whole, a block is added that monitors input/output signals to/from each functional block and determines whether they occur at correct timing, according to the specifications, during the logic simulation. When the logic simulation model runs, the above determination is made.
Meanwhile, there exists a method of describing the interface specifications of functional blocks, for example, the one disclosed in Japanese Patent Laid-Open Publication (Kokai) No. 2000-123064. In this method disclosed, alphabets are assigned to values of signals in combinations passing across a functional block interface and the interface is defined as a set of sequences of alphabets. As the notation of a sequence and the notation of a set of sequences thereof, regular exprssion is used so that a variety of interface definitions can be described by a small quantity of code. Hereinafter, this notation will be referred to as interface notation of Kokai 2000-123064.
As methods for detecting defective or faulty LSIs due to errors in the fabrication process or after the fabrication, a Build-In Self Test (BIST) and an online test are known. These methods provide each LSI with a function of testing for its proper operation. The BIST runs the LSI in test mode different from normal operation and checks for a fault. The online test checks for a fault during normal operation of the LSI. By these test functions, a fault existing in a logical design block of IP can be detected.
After constructing a system LSI by assembling a plurality of functional blocks into the chip, logic simulation has conventionally been applied to verify the functions of the LSI. However, it takes exceedingly much time to complete the logic simulation and this poses a problem that the simulation is usually terminated halfway before verifying all functions. In consequence, there remains a risk that an LSI malfunctions after it is fabricated. If the LSI malfunctions, a defective element causing the malfunction should be located and rectified. When a functional block is suspected to have failed to operate as expected, it must be determined whether the cause is a design error of the functional block thereof or incorrect usage of the functional block thereof causing operation out of its specifications. It must be determined that the object to be rectified is the functional block or an external block using the functional block.
In view hereof, signals appearing at the interface of the functional block should be monitored and the passage of the input/output signals in accordance with the specifications of the functional block should be verified during the logic simulation to be executed before the LSI fabrication. This is accomplished by the interface checking block added to the logic simulation to run. However, it takes exceedingly much time to complete the logic simulation as described above, it is impossible to execute the logic simulation for all possible logic patterns. Thus, the interface cannot be checked completely.
Meanwhile, the above interface checking block aims at the enhancement of the efficiency of logic simulation and therefore its description focuses on only the efficiency of simulation and ignores logic synthesis for installing it on an LSI. Such description does not allow for incorporating its hardware composed of logic circuits into an LSI. Consequently, there has not existed means for locating a design error included in a fabricated system LSI by discriminating between the error of a functional block and the error of an external block using the functional block.
Addressing the above-described challenges, an object of the present invention is to provide means for determining whether any functional block included in a system LSI has a design error or is used by incorrect usage in the event that the system LSI malfunctions after fabricated.
Test data to be used for the above-mentioned BIST and online test as means for detecting a malfunction of a system LSI after its fabrication is generated, based on design data. Even if design data includes an error causing a mulfunction, the test data is generated from it on the assumption that it is correct. This poses a problem that a malfunction due to a design error cannot be detected by the BIST and online test.
The present invention provides means for describing an interface checking block (interface checker) in a hardware description manner in which to allow for logic synthesis, thereby making it possible to incorporate the interface checker into a fabricated system LSI, wherein the interface checker to which the interface specifications described per functional block of the LSI are input determines whether the input/output signals to/from a functional block conform to the interface specifications of the functional block.